Automatic Test Pattern Generator (ATPG) is a design tool that simulates and tests the functionality of individual circuits within an integrated circuit. ATPG generates test vectors for structural testing of the overall functionality of the individual circuits within the integrated circuit. Through the use of real-time clock speed test vectors generated by ATPG, Automatic Testing Equipment (ATE) may provide a particular degree of fault coverage and simulation for the circuitry. ATPG may generate test vectors that detects stuck-at faults, transition faults, path delay faults and other types of faults in circuitry. Conventionally, these test vectors are provided in a computer readable file to the ATE or other testers. The ATE is used in a manufacturing environment to test the die at wafer sort, in packaged tests, and from customer returns. During wafer-level testing of a die, test signals are provided through input or input/output (I/O) bond pads on the die, and the test results are monitored on output or I/O bond pads.
Testing of digital systems, such as the core logic of an integrated circuit, is typically performed by loading a test pattern or stimulus into scanable memory elements in the system, launching the test data into the system, operating the system in normal mode for one or more clock cycles of the system clock, capturing the response of the system to the test stimulus, unloading the test response from the system and then comparing the response to the response which should have been obtained if the system was operating according to design.
To improve test coverage of individual circuits, Design for Testability (DFT) tools have been developed to embed test circuitry into the System-on-Chip (SoC). For example, Built-In Self-Test (BIST) circuitry may be embedded in the integrated circuit design to test individual circuit blocks. BIST circuitry is particularly useful for testing circuit blocks that are not readily accessible through the bond pads of the device under test (DUT). Automated DFT tools may generate BIST circuitry such as memory BIST (MBIST) for testing memory blocks and logic BIST for testing logic blocks. External I/Os directly receive the results of tests conducted by BIST circuitry. In the alternative, external I/Os receive these results indirectly through boundary scan circuitry embedded in the design. Additional internal embedded test circuitry such as scan chain circuitry may also be added to the design to increase the internal testability of internal designs.
Separate embedded test circuitry requires input and output ports that are separate from the input and output ports of the programmed functions. During normal operations, the functional circuitry operates. In the alternative, during the testing mode of operations, a separate set of test circuitry using test inputs and outputs are used. Each core and sub-core embedded on a SoC includes its own test input and output ports and needs to be tested individually, without interference from adjacent cores. Wrapper cell is the circuitry attached to the functional elements of a core to provide paths for test data to flow. The test ports are part of the wrapper cell. Wrapper cell generally includes a flip-flop and a multiplexer, and is able to function in a functional mode and a test mode. In the functional mode, the wrapper cell is transparent and normal functional signals are passed through the multiplexer to the functional core. In the test mode, the wrapper cell changes the input signal causing the test input to be passed through the multiplexer.
Difficulties arise in at-speed testing of systems having multiple clock domains when the clock sources differ from the test clock signal used to perform the test, when these domains have different clock frequencies, and/or when signals crossing the boundary between these clock domains have different clock frequencies. More particularly, it is not uncommon for a SOC integrated circuit (IC) to include several digital modules having a variety of clocking domains and clock frequencies. Since the elements in one domain operate at a different frequency from that of other domains in the system, special provisions must be made during testing to ensure that signals traversing clock domains are synchronized. Synchronization of signals traversing clock domains may be performed by ad hoc clock shaping techniques on some complex SOCs. If signals traversing clock domains are not synchronized, the test response from the system may not be repeatable and test results will be unreliable.
Problems described above of ATPG and BIST based testing techniques may result in need for a testing method and circuitry that enables testing of digital systems at operational clock rate of the system. Such a testing method and circuitry should eliminate problems resulting from multiple clock domains and cover functionality of the SOC device under test (DUT) that is not covered by the ATPG or BIST tests. Furthermore, the testing method and circuitry should also add increased coverage of otherwise unknown and untestable circuitry during production life of the SOC DUT integrated circuit that was not in the original ATPG or BIST design-for-test coverage.